This invention relates to a charge transfer device and a solid state image pickup device using a charge transfer device.
Heretofore, a solid state image pickup device called an accordion imager has been known. This device is described in detail on pages 40 to 43 in the Technical Digest at the International Electron Device Meeting in 1984. A conventional accordion imager is shown in FIG. 20. This imager includes six charge transfer devices 1 arranged in parallel, 20 transfer electrodes 2, per each charge transfer device constituting respective transfer devices, a shift register 3, two-phase control pulse supply lines 4 and 5 for controlling the shift operation of the shift register, and transfer pulse supply lines 6 for delivering outputs from the shift stages as transfer pulses to corresponding transfer electrodes, respectively. Each charge transfer device 1 functions as photoelectric conversion elements to store or accumulate, for a predetermined time, carriers generated by light incident to the transfer channel through the electrodes 2 and transfer them.
This operation will be described in detail in conjunction with FIG. 21. In FIG. 21(a), reference symbols S.sub.1 to S.sub.12 represent respective shift stages, reference numeral 7 an input terminal for inputting a transfer control pulse to the shift register, and reference symbols E.sub.0 to E.sub.11 respective transfer electrodes when one of a plurality of charge transfer devices is taken out. Further, the slanting line portions represent the state where signal charges are stored below the transfer electrodes (the electrode voltage corresponds to high level which will be referred to as H level hereinafter, respectively, and non-slanting line portions represent the state no signal charge is stored below the transfer electrodes (the electrode voltage corresponds to low level which will be referred to as L level), respectively. In addition, reference symbols A.sub.1 to A.sub.15 represent transfer states at respective times after the transfer operation is initiated. Reference symbols .PHI..sub.1 and .PHI..sub.2 denote shift register control pulses of first and second phases, respectively. Such a two-phase clock pulse is conventionally used. Reference symbol PI denotes a transfer control pulse inputted to the shift register. As shown in FIG. 22, each of shift stages S.sub.1 to S.sub.12 comprises a sample hold circuit comprised of a MOS transistor 11a and a capacitor 11b, and an inverter 12. When a pulse of L level is inputted as the transfer control pulse PI, a signal of H level is outputted. Namely, a signal is inverted every time it is shifted by one stage and the inverted signal is transmitted to the succeeding stages. Accordingly, when the shift register continues to be operated under the state where the transfer control pulse PI is held at L level, the transfer state of A.sub.1 lasts, so H level is held every other electrode. In this state, where carriers produce by photo conversion are stored, one pixel is formed by two electrodes in a vertical direction. In the example of FIG. 21, six pixels are formed. After storage operation for a predetermined time is completed, when the transfer control pulse PI shifts to H level, the electrode E.sub.0 is placed at H level. As a result, signal charge Q.sub.1 moves to the portion below two electrodes extending from E.sub.1 to E.sub.0, resulting in the state of A.sub.2.
When a control pulse .PHI..sub.2 is applied at time t.sub.3, the shift stage S.sub.1 becomes operative. As a result, a transfer control pulse PI of H level is inverted and that inverted pulse is transmitted to the electrode E.sub.1. Thus, the electrode E.sub.1 is placed at L-level, so signal charge Q.sub.1 moves from the electrode E.sub.1 to E.sub.0, and predetermined other devices succeeding thereto (e.g., a horizontal transfer device) (state of A.sub.3). When the transfer control pulse PI shifts to L level, the electrode E.sub.0 is placed at L level. When the control pulse .PHI..sub.1 applied at time t.sub.4, L level of the electrode E.sub.1 moves to the electrode E.sub.2 as H level inverted by the shift stage S.sub.2, resulting in the state of A.sub.4. The signal charge Q.sub.1 has completed transfer from the transfer device 1 to other devices, and a portion of the signal charge Q.sub.2 moves to the portion below the electrode E.sub.2. Subsequently, when the control pulse .PHI..sub.2 is applied, potential levels of the shift stages S.sub.1 and S.sub.3 are inverted, resulting in the state of A.sub.5. As a result, signal charge Q.sub.1 moves to the portion below the electrodes E.sub.1 and E.sub.2. At this time, the electrode E.sub.3 is placed at L level. Thus, transfer of signal charges Q.sub.1 from the electrode E.sub.3 is completed.
Subsequently, when the transfer control pulse PI shifts to H level and the control pulse .PHI..sub.1 is applied at time t.sub.6, there results the state of A.sub.6. Namely, the electrode E.sub.4 is placed at H level by the level inversion of the shift stage S.sub.4. As a result, signal charge Q.sub.3 moves to the portions below the electrodes E.sub.4 and E.sub.5, and signal charge Q.sub.2 moves to the portions below the electrodes E.sub.0 and E.sub.1 by the level inversion of the shift stage S.sub.2 by the transfer control pulse PI.
When the control pulse .PHI..sub.2 is applied at time t.sub.7, there occur level inversions of the shift stages S.sub.1, S.sub.3 and S.sub.5, resulting in the state of A.sub.7. Subsequently, when the transfer control pulse PI shifts to L level and the control pulse .PHI..sub.1 is applied at time t.sub.8, levels of the shift stages S.sub.2, S.sub.4 and S.sub.6 are inverted, resulting in the state of A.sub.8. Thus, signal charge Q.sub.2 has been completely transferred from the transfer device to other devices. By repeating such an operation, signal charges Q.sub.3, Q.sub.4, Q.sub.5 and Q.sub.6 are transferred. Thus, all signal charges can be transferred to other devices.
This charge transfer process in this prior art is similar to the transfer process of a well known four-phase driven charge transfer device constructed to store charges below two electrodes and transfer them. However, this prior art differs from the four-phase driven charge transfer device in the following ways. First, in the case of the four-phase driven charge transfer device, since a common transfer pulse is applied every four electrodes, it is unable to independently transfer signal charges stored below every other electrode by a four-phase drive in sequence. Namely, since a pixel must be formed using four electrodes as one set, only three pixels are formed in a vertical direction in the case of the number of electrodes of FIG. 21. Accordingly, the degree of integration of pixels is one half of that of the above-mentioned prior art. Secondly, since phases of four pulses can be arbitrarily set in general in the case of the four-phase driven charge transfer device, a four-phase type maximum transfer charge quantity available in principle can be transferred.
On the other hand, in the case of the conventional accordion type charge transfer device, it is impossible to arbitrarily set inversion timings of H level and L level, inverted at every other electrode. Thus, the transfer ability of the four-phase type cannot be necessarily utilized.
This will be described with reference to FIGS. 23, 24 and 25.
FIG. 23 shows electrodes E.sub.2 to E.sub.10 connected to output stages S.sub.2, . . . S.sub.10 of the shift register, respectively, and FIG. 24 shows a potential distribution in charge transfer channels below corresponding electrodes. As shown in FIG. 21, at time t.sub.6, electrodes E.sub.2 and E.sub.3 are placed at L level, electrodes E.sub.4 and E.sub.5 are placed at H level, and electrodes E.sub.6, E.sub.7, E.sub.8, E.sub.9, E.sub.10 are set so that they are at L level and H level one after another. In accordance with this, potentials of L level and H level of the transfer channel are formed as shown in FIG. 24 (t.sub.6) Thus, signal charges Q.sub.3, Q.sub.4 and Q.sub.5 are stored into the portions of H level. Since a maximum quantity of charges which can be stored and transferred prescribes the upper limit of the dynamic range, it is preferable that such a quantity is as large as possible. Further, since a quantity of charges which can be stored is substantially proportional to the electrode area, it is preferable that the charge storage state, i.e., the areas of the electrodes E.sub.1, E.sub.3, E.sub.5, E.sub.7, E.sub.9 and E.sub.11 set to H level before time t.sub.2 are set to a relatively large value.
In the case where such a setting is made, at time t.sub.7, if the electrode E.sub.3 is first inverted to H level and the electrode E.sub.5 is then inverted to L level, the merit of the four-phase drive can be utilized, resulting in no problem. However, the above-mentioned two operations are carried out at the same time in principle in the prior art. Let now consider the case where the rise time t.sub.r of the circuit constituting respective output stages of the shift register is large and the fall time t.sub.f thereof is small. The transfer pulse waveforms of respective output stages in this case is shown in FIG. 25. At time t.sub.7, the output of the shift stage S.sub.5 is already inverted to L level, but the output of the shift stage S.sub.3 is not yet inverted to H level. Accordingly, as shown in FIG. 24 (t.sub.7), the electrodes E.sub.3 and E.sub.5 adjacent to the electrode E.sub.4 having a small area are placed at L level. At this time, signal charge Q.sub.3 of which quantity is larger than a quantity of charges which can be stored only below the electrode E.sub.4 overflows below the electrode E.sub.4 and diffuses into the portion below electrodes of H level close thereto. .DELTA.Q.sub.3 shown in FIG. 24 (t.sub.8) shows a portion of signal charge Q.sub.3 which overflows up to the electrode E.sub.7 and is mixed with signal charge Q.sub.4. Such a phenomenon will occur with respect to signal charge Q.sub.4 at time t.sub.10 shown in FIG. 24 (t.sub.10), and will occur eventually with respect to all charges. In other words, in the case of the conventional accordion type charge transfer device, where a relative difference between the electrode areas is provided as shown in FIG. 23, the ability of the charge transfer device would be lowered. Accordingly, equally setting the areas of all the electrode results in a best structure. Namely, a maximum quantity of transfer charges cannot be larger than one half of that corresponding to all the area of the two electrodes. It has been described that the rise time t.sub.r of the output stage of the shift register and the fall time t.sub.f thereof are assumed to be expressed as t.sub.r &gt;t.sub.f. However, generally in the case Of a complementary MOS inverter circuit (see FIG. 13) used at the output stage, a p-type channel transistor prescribing the rise time has a mobility smaller than that of an n-channel transistor prescribing the fall time. Ordinarily, the relationship expressed as t.sub.r &gt;t.sub.f holds. In addition, when the fact that it is very difficult to conduct a waveform control because of large unevenness of a load capacity of the electrodes and unevenness of the resistance over the entire transfer device is taken into consideration, it is difficult to realize an ideal four-phase drive using the conventional accordion type charge transfer device.